The present invention relates generally to magnetroresistive random access memory (MRAM), and more particularly to core structure designs of the MRAM.
MRAM combines magnetic memory elements with standard silicon-based integrated circuits to obtain the combined attributes of non-volatility, high-speed operation and unlimited read and write endurance not found in any other existing memory technology. Each memory element in a MRAM uses a magnetic tunnel junction (MTJ) device for data storage. The MTJ is composed of a fixed magnetic layer set to a particular polarity, a thin dielectric tunnel barrier, and a free magnetic layer with a field changes to match that of an external field. When a bias is applied to the MTJ, electrons that are spin polarized by the magnetic layers traverse the dielectric barrier through a process known as tunneling. The MTJ device has a low resistance when the magnetic moment of the free layer is parallel to the fixed layer and a high resistance when the free layer moment is oriented anti-parallel to the fixed layer moment.
FIG. 1 shows a conventional 1-transistor, 1-magnetic-tunnel junction (1T1MTJ) MRAM cell 100. A MTJ 102 is sandwiched between two write lines (WLs) 110 and 115. When currents with right timing run through both the WLs 110 and 115, the field of the fixed magnetic layer in the MTJ 102 can be altered, therefore a desired data is written into the MTJ 102. The MTJ 102 is read by measuring its resistance. One way to measure the resistance is to turn on a NMOS select transistor 120 and let a reference current 125 pass through the MTJ 102, a resulting voltage from the MRAM cell 100 is compared with a reference cell (not shown) to get a logic “1” or “0” reading.
Unlike most other semiconductor memory technologies, the data is stored in the MRAM as a magnetic state, rather than charge, and sensed by measuring the resistance without disturbing the magnetic state. Using a magnetic state for storage has two main benefits: (1) The magnetic polarization does not leak away with time like charge does, so the information is stored even when the power is turned off; and (2) switching the magnetic polarization between the 2 states does not involve actual movement of electrons or atoms and thus has no known wear-out mechanism.
“Toggle” approach is using the same pulse sequence to write from logic “0” state to “1” state, and for “1” state to “0”. Each time the sequence is executed the device changes from its current magnetic state to the opposite state. This type of switching is significantly different from the simple type of switching where the magnetic moment of the free layer simply follows the applied field. When using the toggle writing method, there is a need to determine the initial state of the MRAM device before writing, because if the initial state is the same as the target state, no toggling will be need, otherwise, a toggling will be performed on the MRAM device.
FIG. 2 illustrates a toggle mode MRAM cell 200 that utilizes a unique behavior of a synthetic antiferromagnet (SAF) free-layer 320 formed from two ferromagnetic layers 322 and 328 separated by a non-magnetic coupling spacer layer 325. The magnetic moments of the SAF free-layer 320 switch between two states when the proper magnetic field sequence is applied. The MRAM cell 200 comprises a SAF fixed layer 340 formed also from two ferromagnetic layers 342 and 348 separated by a non-magnetic coupling spacer layer 345. A tunnel barrier 330, made of alumina (AlOx) for instance, is sandwiched between these two SAF layers 320 and 340. The SAF layers 320 and 340 and the tunnel barrier 330 form the core of the tri-layer MRAM cell.
Referring again to FIG. 2, the bottom ferromagnetic layer 328 of the SAF free-layer 320 is often called a sense layer, and the top ferromagnetic layer 342 of the SAF fixed layer 340 is often called a reference layer. Electrons tunnel across the alumina tunnel barrier 330, resulting in a magnetoresistance that is sensitive to the magnetic moment direction of the sense layer 328 relative to the reference layer 342. The moment-balanced SAF free-layer 320 responds to an applied magnetic field differently than the single ferromagnetic layer of conventional MRAM. Rather than following an applied magnetic field, the two antiparallel layer magnetizations will rotate to be approximately orthogonal to the applied field. A current pulse sequence is used to generate a rotating magnetic field that moves the free-layer moments through the 180-degree switch from one state to the other, as shown in FIG. 3, wherein magnetic fields, H1, (H1+H2) and H2, are produced by passing currents, i1 and i2, through write line1 and write line2, respectively.
FIG. 4 illustrates the toggle write mode for writing a “1” to a “0” using current pulse sequence. In this illustration at time t0, magnetic moment vectors are oriented in the preferred directions. This orientation will be defined as a logic “1”.
At a time t1, a positive write word current is turned on, which induces H1 to be directed in the positive y-direction. The effect of positive H1 is to cause the nearly balanced anti-aligned MRAM tri-layer to orient toward the applied field direction. The finite anti-ferromagnetic exchange interaction between ferromagnetic layers (top free-layer 322 and bottom free-layer 328, see FIG. 3) will allow magnetic moment vectors to now deflect at a small angle toward the magnetic field direction and resultant magnetic moment vector (H2) will subtend the angle between magnetic moment vectors and will align with H1. Hence, magnetic moment vector of the bottom free-layer 328 is rotated in clockwise direction. Since resultant magnetic moment vector is the vector addition of magnetic moment vectors, magnetic moment vector is also rotated in clockwise direction.
At a time t2, positive write bit current is turned on, which induces positive direction on an easy axis which is at a 45° angle relative to the positive y- and positive x-directions. Consequently, resultant magnetic moment vector is being simultaneously directed in the positive y-direction by H1 and the positive x-direction by the direction of H1 and H2, which has the effect of causing effective magnetic moment vector to further rotate in clockwise direction until it is generally oriented at a 45° angle between the positive x- and positive y-directions. Consequently, magnetic moment vectors will also further rotate in clockwise direction.
At a time t3, write word current is turned off so that now only H2 is directing resultant magnetic moment vector, which will now be oriented in the positive x-direction. Both magnetic moment vectors will now generally be aligned with respect to this magnetic field.
At a time t4, write bit current is turned off so a magnetic field force is not acting upon resultant magnetic moment vector. Consequently, magnetic moment vectors will become oriented in their nearest preferred directions to minimize the energy. In this case, the preferred direction for magnetic moment vector is at a 45° angle relative to the positive y- and positive x-directions. This preferred direction is also 180° from the initial direction of magnetic moment vector at time t0 and is defined as “0”. Hence, the MRAM cell has been switched to a logic “0”.
FIG. 5 is a schematic diagram illustrating a plurality of the MRAM cells 200 arranged in an array with each write line spanning hundreds or even thousands of bits in making a conventional high density MRAM 500. Each MRAM cell 200 is serially connected with a NMOS select transistor 120 forming a storage unit 502. For reading, each storage unit 502 is connected to a read-word-line (RWL) 510 and a read-bit-line (RBL) 515, wherein the RWL 510 is connected to a gate of the NMOS select transistor 120, and the RBL 515 is connected to a drain of the NMOS select transistor 120. During a read operation, a select transistor 120 of a target storage unit 502 is turned on to bias the corresponding MRAM cell 200 and a resulting current is compared to a reference to determine if a resistance state of the target MRAM cell 200 is the logic “0” or “1”. For writing, a write-word-line (WWL) 520 runs through a row of the MRAM cells 200, and a write-bit-line (WBL) 525 runs through a column of the MRAM cells 200. During a write operation, current pulses are passed through the WWL 520 and WBL 525 writing only the MRAM cell 200 at the cross point of the WWL 520 and WBL 525.
Referring again to FIG. 5, with the select transistor 120, each individual storage unit 502 in the conventional MRAM 500 is directly readable. However, the numerous select transistors 120 and the RBLs 515 has a penalty on the die size, and hence the cost of the conventional MRAM 500.
As such, what is desired is a MRAM array architecture with reduced components, yet still maintains accessibility to each individual cells.